RISC-V and Low-End Disruption

In his widely circulated post RISC-V: They Should Have Known Better, engineer Dmitry Grinberg delivers a devastating technical teardown of the emerging architecture: the RISC-V standard, he argues, is riddled with fundamental design compromises. It enforces objectively worse code density, misses obvious addressing modes that have been standard for decades, and locks in architectural decisions that make high-performance implementations unnecessarily complex. They traded engineering elegance for ideological purity.

Over on Hacker News, commentators celebrated the engineering rigor. The prevailing sentiment was sharply critical of the new protocol: the industry is throwing away decades of instruction set optimizations just to avoid paying ARM's licensing fees, baking in technical debt that will ultimately hold the entire sector back.

To be clear, the commentators are right to applaud the rigorous breakdown. The analysis is mathematically sound, and Grinberg is entirely accurate on the specs. This technical inferiority, though, is the defining precondition for Clayton Christensen’s theory of low-end disruption.

To understand why, you have to walk the real economics of the silicon IP market, long before you introduce any theoretical abstraction.

The value chain for any given semiconductor market is effectively divided into IP creation, chip design, manufacturing, and the final device. For decades, the dominant paradigm in chip design has been deeply integrated. ARM, the reigning incumbent, spends billions of dollars developing both the Instruction Set Architecture (ISA) and the specific microarchitecture cores that implement it. They monetize this integration through a highly defended tollbooth: if a company wants to build a chip using an ARM core, they pay an upfront licensing fee, followed by an ongoing per-chip royalty. That royalty, which often scales directly with the volume and value of the shipped silicon, protects ARM's incredibly lucrative margins and funds the massive R&D budget required to build the next generation of bleeding-edge performance.

Here is an explicit scenario: imagine a hardware startup building a fleet of connected industrial sensors. If they choose ARM, they must navigate a legal negotiation, commit to upfront fees, and sign away a few cents on every single unit they ever ship. On a high-end smartphone processor, those cents are a rounding error; on a two-dollar embedded microcontroller, they are a significant tax on a fundamentally commoditized value chain.

RISC-V, by contrast, is a standard protocol, meaning its real economic lever is zero financial and legal transaction costs. There is no central authority extracting a royalty, no mandatory upfront licensing negotiation, and no ongoing legal friction dragging down the cash conversion cycle of a volume-heavy, low-margin device maker. You simply download the ISA, implement it in your own core (or license a modular core from a third party), and ship your product. The truest cost advantage is not merely a $0 bill of materials, but the total removal of the integrated tollbooth.

This dynamic is exactly what Clayton Christensen mapped out in The Innovator's Dilemma. The framework plots two distinct trajectories on a graph. Imagine the visual: the pace of technology improvement forms the Y-axis, advancing over time on the X-axis, plotted directly against the trajectory of actual market need.

The incumbent’s line starts high and angles aggressively upward. Driven by the rational pursuit of higher margins and demanding customers, they march relentlessly upmarket. They build increasingly sophisticated, integrated products that eventually over-serve the needs of the low end. ARM has spent a decade doing exactly this, optimizing for Apple, Qualcomm, and data centers, pushing the boundaries of performance-per-watt to command premium royalties.

Meanwhile, the entrant’s line starts fundamentally below the threshold of acceptability. The entrant introduces a modular alternative that is, by any strict technical definition, worse. Yet it is "good enough" for the least demanding tiers of the market, and it competes on a completely different vector, typically price, convenience, or in this case, the total elimination of transaction friction. The entrant captures the undefended, low-margin floor of the market, generating the volume and ecosystem scale needed to steadily improve its technology until it inevitably angles upward to challenge the core business.

We can see this embedded floor being captured perfectly in real time.

Consider companies that prioritize economics over technical purity, such as Espressif with the ESP32-C3 or the custom storage controllers built internally by Western Digital. Neither company switched to RISC-V because they were chasing technical elegance or seeking superior code density. They switched because controlling their own destinies made overwhelmingly better business sense. They are building precisely what they need, for low-margin environments where fractions of a cent matter, without paying an ongoing toll to an integrated incumbent. The technical compromises of the ISA are easily absorbed by the absolute economic superiority of a zero-cost protocol.

ARM’s response to this bleeding floor is the textbook incumbent reaction. Recognizing the threat at the low end, they introduced the Cortex-M0 and launched Flexible Access programs. These are desperate attempts to reduce upfront friction and keep embedded developers inside the ARM ecosystem.

Notice the structural bind, though: ARM is entirely willing to lower the initial barrier to entry (you can start designing without paying upfront fees), but they are fatally clinging to the integrated royalty model on the back end. They cannot abandon the very tollbooth that defines their business model, which means they can never truly match the zero-transaction-cost reality of an open protocol. They are over-serving the top and stranded at the bottom.

The solipsism of purely technical critiques is that they miss this entirely.

The final phase of Christensen's model is the inevitable march upmarket. The entrant, fueled by the sheer volume of deployments at the low end, attracts toolchain developers, compiler optimizations, and robust software ecosystems. Software ecosystems are notoriously sticky; developers write code for the hardware that exists in volume. As billions of cheap RISC-V cores flood the embedded market, the operating systems adapt, and the entire open-source community inadvertently subsidizes the R&D required to move the standard upmarket. The technology improves until it crosses the threshold of high-end performance.

This brings us to the newly ratified RVA23 profile. This profile standardizes vector cryptography, hypervisor extensions, and advanced memory management for the architecture. To put it another way, RISC-V is moving out of low-end microcontrollers and directly into high-end compute, right up ARM's value chain.

The engineering rigor of pointing out design compromises is valuable, and the code density metrics are mathematically sound. The reality, though, is that software ecosystems follow the money. Market dominance is driven by structural cost advantages, not mathematically flawless instruction sets. The market does not reward technical perfection — a reality that reliably breaks the hearts of hardware engineers — but instead rewards "good enough" modularity that structurally alters the cost of doing business. An inferior but zero-transaction-cost protocol will inevitably modularize the ISA layer from the bottom up.

This shift to an open standard represents a generational realignment for semiconductors, but hardware cycles play out over agonizingly long timelines. The structural vector is clear: a zero-cost modular protocol will relentlessly squeeze the integrated incumbent from the bottom up. Exactly when it fully displaces ARM at the highest tiers of performance, however, remains a much longer bet.